BECKHOFF CB4055 - Handbuch (Seite 59)

Chipset Kapitel: BIOS-Einstellungen
Beckhoff New Automation Technology CB4055 Seite 59
5.4.1.1 PCI Express Configuration
Aptio Setup Utility - Copyright (C) 2011 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Configuration │Enable or disable PCI Express │
│ │Clock Gating for each root │
│ PCI Express Clock Gating [Enabled] │port. │
│ DMI Link ASPM Control [Enabled] │ │
│ DMI Link Extended Synch Control [Disabled] │ │
│ PCIe-USB Glitch W/A [Disabled] │ │
│ Subtractive Decode [Disabled] │ │
│ │ │
│► PCI Express Root Port 1 │ │
│► PCI Express Root Port 2 │ │
│► PCI Express Root Port 3 │ │
│► PCI Express Root Port 4 │ │
│ PCIE Port 5 is assigned to LAN │────────────────────────────────│
│ PCIE Port 6 is assigned to LAN2 │→←: Select Screen │
│ │↑↓: Select Item │
│ │Enter: Select │
│ │+/-: Change Opt. │
│ │F1: General Help │
│ │F2: Previous Values │
│ │F3: Optimized Defaults │
│ │F4: Save & Exit │
│ │ESC: Exit │
│ │ │
│ │ │
│ │ │
│ │ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.14.1219. Copyright (C) 2011 American Megatrends, Inc.
ü PCI Express Clock Gating
Optionen: Disabled / Enabled
ü DMI Link ASPM Control
Optionen: Disabled / Enabled
ü DMI Link Extended Synch Control
Optionen: Disabled / Enabled
ü PCIe-USB Glitch W/A
Optionen: Disabled / Enabled
ü Subtractive Decode
Optionen: Disabled
ü PCI Express Root Port X
Untermenü: siehe "PCI Express Root Port" (p. 60)